Exercise 10.4 - SysML to Simulink with Buses and Library Blocks

Owned by Ambarish Ganesh (Unlicensed)
Last updated: Oct 06, 2022 by Rose Yntema
6 min read

Objectives

The new learning objective of this exercise is to generate a Simulink model from a SysML block structure. This model has several features not shown in Exercise 10.4, including

  • A multilevel block structure

  • Buses

  • Library Blocks

  • Flow Ports

Preparation

This exercise assumes the student has

Example – SysML to Simulink

Figure 1 SysML Starter Model, System block IBD

The SysML model used in this exercise is found in the Simulink_Tutorial Part 3 package in the Syndeia Tutorial Testbed.mdzip project. The SysML diagram shown in Figure 1 is the top level of a multi-level model and parts pA, pB, and pC all contain internal structure, for example, the second-level structure of PartC is shown in Figure 2 and the third-level structure of PartC1 is shown in Figure 3.

Figure 2 SysML Starter Model, PartC block IBD
These SysML diagrams also show some special features:

  • Simulink Library Blocks – Simulink has a library of special blocks that carry out specific functions, e.g. mathematical, logical and signal processing operations. A equivalent library can be created in SysML that Syndeia recognizes by their <<Simulink Library Block>> stereotype. See the Appendix for this exercise and multiple examples in the Simulink LibBlocks package. The parts of type Gain and Not in Figure 1 are examples.

  • Buses – In Simulink, connectors called buses carry multiple signals that can be multiplexed/demultiplexed and routed separately to and from different blocks. It is necessary to create additional blocks that demultiplex (Bus Selector) or multiplex (Bus Creator) multiple flows on a single connector. These also have the <<Simulink Library Block>> stereotype and several are shown in Figure 1.

  • Flow Ports – Although deprecated in the SysML standard, these are still found in many older SysML models and Syndeia supports them the same as proxy and full ports in model transforms to and from Simulink. These

    Figure 3 SysML Starter Model

Exercise

  1. Open Syndeia Tutorial Testbed.mdzip (get it here - https://intercax.atlassian.net/wiki/spaces/SYN34/pages/2407364009) and launch the Syndeia dashboard from the Simulink_Tutorial Part 3 package. Select a Syndeia Cloud project, if required.

  2. In the Settings tab, as shown in Figure 4, select the desired options for the SysML-to-Simulink transformation. For example, we chose to perform the transform recursively to deeper and deeper levels of SysML blocks.

    Figure 4 Syndeia Settings tab

  3. In the Connection Manager tab, load the SysML model in the left column, the local repository connection in the right (Dirk Local in this example), and select Model Transform connection type in the middle column). Drag-n-drop the System block to a folder in the local file system repository. Review Exercise 10.1 for this operation.

  4. Open the System.slx model in Simulink. After some rearrangement, it should appear similar to Figure 5. A Simulink model was generated equivalent to the System block structure. Part properties pA, pB, and pC of the System block were generated as model references with the same name in the Simulink model. Special Simulink Library blocks bs1, g1, n1 and bc1 were also created. Full, proxy and flow ports within the System block were generated as Simulink ports, and connectors were generated as lines with signal flows.

    Figure 5 Simulink model structure generated from SysML block structure for System block

  5. Double-click on the PartC block in the System Simulink model. This will open the newly generated PartC model in Simulink, as shown in Figure 6 below—after re-arranging the layout to match SysML IBD in Figure 2.

    Figure 6 Simulink model structure generated from SysML block structure for PartC block

  6. Double-click on the PartC1 block in the PartC Simulink model. This will open the newly generated PartC1 model in Simulink, as shown in Figure 7 below—after re-arranging the layout to match SysML IBD in Figure 3.

    Figure 7 Simulink model structure generated from SysML block structure for PartC1 block

  7. Model transform also works in the opposite direction, from Simulink to SysML. The settings shown in Figure 4 map Simulink ports to proxy ports in SysML and call for Simulink library blocks to be included in the model transform. Create an empty package in your SysML model and drag the Simulink System block into the package. Compare the newly generated PartC1 model in SysML, as shown in Figure 8 with the original SysML IBD in Figure 3. In particular, a new set of <<Simulink Library Blocks>> are created in SysML with names and properties different than the originals in the Simulink_Tutorial Part 3 package.

    Figure 8 SysML model structure generated from Simulink block structure for PartC1 block

  8. Modify the System block in the Simulink_Tutorial Part 4 package in the SysML model by deleting the pA.PartA part property and its associated connectors. Execute a Compare Source and Target operation across the System-System connection. Results should be similar to Figure 9.

    Figure 9 Comparison Results after deleting pA from System SysML block

  9. Execute a Sync Target -> Source operation across the System-System connection. This should restore the pA.PartA part property and its associated connectors. Repeat Compare Source and Target operation to confirm.

CAUTION: Some versions of MagicDraw create an erroneous validation error when delegation connectors are added to the SysML model via Syndeia. It may be necessary to redraw the IBD diagram after syncing to reset the error warning.

Appendix

Follow the general rules below to define a Simulink library block in SysML. Examine the blocks in the Simulink LibBlocks package as examples.
A1. Create a SysML block or activity, and assign it the Simulink_Library_Block stereotype available in the Syndeia profile.
A2. Add a value property (for SysML blocks) or property (for SysML activities in MagicDraw) called name and typed by the String value type. The default value of this property must be the exact name of the Simulink library block in the Simulink library. 
A3. Similarly, you may add other properties as required when using the Simulink library blocks, e.g. Add block uses a property Input with value ++ to indicate addition of two input arguments.
A4. The input and output ports must be numbered in ascending alphanumeric manner, ending with numbers 1, 2, 3, and so on. For example, input ports on a Simulink library block must be named in1, in2, in3, etc. and output ports on a Simulink library block must be named out1, out2, out3, etc.
A5. The ports may be flow, proxy or full ports to represent the inputs and output of a Simulink library block. If flow ports, the port types should be primitive value types (Real, Integer, Boolean). If proxy ports, their interface blocks should contain flow properties typed by primitive value types. If full ports, the blocks serving as their types should contain flow properties typed by primitive value types.