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Exercise 10.6 - Simulink -> SysML with model generation level settings

Exercise 10.6 - Simulink -> SysML with model generation level settings

Objective

This tutorial demonstrates Simulink to SysML model generation level using the model generation and compare/sync between SysML and Simulink models. The three settings are as follows:

SysML from/to Simulink model generation level

Sets the level of model generation and compare/sync between SysML and Simulink models. The three settings are as follows:

(1) SIMPLE

  • SysML → Simulink: Generate a Simulink model based on the SysML Block/Activity. Only ports are generated. No internal structure is generated.

  • Simulink → SysML: Generate a SysML Block/Activity based on the Simulink model. Only ports are generated. No internal structure is generated.

(2) IMMEDIATE

  • SysML → Simulink: Generate a Simulink model based on the SysML Block/Activity. Simulink model will have ports corresponding to the SysML Block/Activity, and Simulink blocks and signal/bus flows corresponding to the immediate structure (1 level only) of the SysML Block/Activity, i.e. immediate part/reference/shared properties of the SysML Block, or immediate call behavior actions of the SysML Activity.

  • Simulink → SysML: Generate a SysML Block/Activity based on the Simulink model. SysML model will have ports (or pins) corresponding to the Simulink model, and part properties (or call behavior actions) and connectors (or object flows) corresponding to the immediate blocks (1 level only) and signal/bus flows in the Simulink model.

(3) RECURSIVE (default)

  • SysML → Simulink: Generate a Simulink model based on the SysML Block/Activity. Simulink model will have ports corresponding to the SysML Block/Activity, and Simulink blocks and signal/bus flows corresponding to all the part/reference/shared properties (or call behavior actions) in the multi-level SysML Block/Activity hierarchy.

  • Simulink → SysML: Generate a SysML Block/Activity based on the Simulink model. SysML model will have ports (or pins) corresponding to the Simulink model, part properties (or call behavior actions), and connectors (or object flows) corresponding to all the blocks in the multi-level Simulink model hierarchy.

Preparation

This exercise assumes the student has

  • Cameo System Modeler 18.0 - 19.0 (or MagicDraw with SysML plug-in) installed correctly on his or her machine with a valid license for use.

  • Syndeia 3.3 installed as a plugin for Cameo/MagicDraw with a valid license for use.

  • Syndeia Simulink interface, correctly installed with a valid license for use.

  • MATLAB/Simulink R2016b or later installed correctly on his or her machine with a valid license for use.

  • In this tutorial, we will use the Simulink Model developed Exercise 10.5 - SysML -> Simulink with model generation level settings in Demonstration 3 using Recursive settings.

This model will be sent to SysML using the three settings of Simple, Immediate, and Recursive.

The Simulink model is shown here.

Figure 1: System Model in Simulink

The Target SysML Model and Package are in Syndeia_Simulink_Examples.mdzip (get it here - SysML Models, Profiles and Mappings) as shown here.

Figure 2: Target SysML model and packages

Demonstration 1: Simple Settings

1A) Select SysML type: Full Port

1 Set SysML port type when generating from Simulink setting to FULL_PORT under MATLAB/Simulink category in Syndeia settings, and click the Apply button.

Figure 3: Syndeia Settings tab

2 In Syndeia dashboard perform Model Transformation. Send System.slx to SysML Package From_Simulink>Simple>FullPort

Figure 4: Model Transform System from Simulink to SysML to generate internal block structure

3 Updated SysMl package with data from Simulink

Figure 5: SysML blocks and full ports created from Simulink

4 Now go to the Connections Search Tab in Syndeia and Click Get All to see the connections. Select Compare Source and Target.

Figure 6: Comparing Source and Target from Connection Search Tab

5 Ports are shown on both SysML as well as Simulink. This can be seen in the Comparison Result tab as shown below.

Figure 7: Comparison result

6 Now in Simulink Model we add a new port ‘p1’ and remove the port in1 and further replace ‘in1’ with p1.

So Part A has p1 coming in.

Figure 8: Making changes in the Simulink model

7 Again going to Connections Search Tab in Syndeia, Compare the connection. The Comparison Result will be shown below.

Figure 9: Comparison result showing mismatch between ports in Simulink and SysML

8 Here p1 is shown on Simulink Side and in1 in on the SysML side.

9 Now in the Connections Search tab select Sync Target and Source on the connection.

Figure 10: Syncing Target to Source from Connection Search tab

10 Again in the Connection Search tab do Compare the connection. The Comparison Result will show the result below.

Figure 11: Comparison result

11 Observe p1 is appeared both on SysML and Simulink side.

12 In SysML MagicDraw Model it is seen as below.

Figure 12: SysML model updated

1B) Generate SysML blocks with Proxy Ports and Apply

1 Set SysML port type when generating from Simulink setting to PROXY_PORT under MATLAB/Simulink category in Syndeia settings, and click the Apply button.

Figure 13: Syndeia Settings tab

2 In the Syndeia dashboard perform Model Transformation. Send System.slx to SysML Package From_Simulink>Simple>ProxyPort

Figure 14: Model transform System Simulink model to SysML package From_Simulink::Simple::ProxyPort

3 In Syndeia it appears as below.

Figure 15: New System block and proxy ports shown in Syndeia dashboard

4 Do Compare in the Connection Search tab for the connection, it appears as Proxy Port as shown below.

Figure 16: Comparison result

5 In SysML Containment Tree it is seen as Proxy Port as shown below.

Figure 17: New System block and proxy ports shown in SysML containment tree

Demonstration 2: Immediate Settings

2A) Generate SysML blocks with Full Ports and Apply

1 Set SysML port type when generating from Simulink setting to FULL_PORT under MATLAB/Simulink category in Syndeia settings, and click the Apply button.

2 Apply Settings as shown here.

Figure 18: Syndeia Settings tab

3 In Syndeia dashboard select the System.slx and perform Model Transformation to SysML Package From_Simulink>Immediate Package>FullPort

Figure 19: Model Transformation to SysML package From_Simulink::Immediate Package::FullPort

4 In Syndeia Dashboard it appears as below.

Figure 20: Syndeia Dashboard showing blocks generated in SysML

5 In the Connections Search tab select Get All. Now all new connections are generated as shown. Do Compare Source and Target as shown below.

Figure 21: Compare Source and Target from Connection Search tab

6 In the Comparison Result tab this shows as below.

Figure 22: Comparison result

7 In SysML Magicdraw this looks as showing Full Ports.

Figure 23: New blocks and full ports shown in SysML containment tree

2B) Generate SysML blocks with Proxy Ports and Apply

1 Set SysML port type when generating from Simulink setting to PROXY_PORT under MATLAB/Simulink category in Syndeia settings, and click the Apply button.

Figure 24: Syndeia Settings tab

2 Perform Model Transform in Syndeia Dashboard. Send System.slx to SysML Package From_Simulink>Immediate>ProxyPort

Figure 25: Model transform of System Simulink model to SysML package From_Simulink::Immediate::ProxyPort

 

3 In Syndeia Dashboard in Connection Manager tab, this appears as below.

Figure 26: New blocks and proxy ports shown in Syndeia dashboard

 

4 Now in the Connection Search tab click Get All. This will show all connections generated. Select Compare Source and Target on the connection as shown below.

Figure 27: Compare Source and Target from Connection Search tab

5 In the Comparison Result tab the result is shown below.

Figure 28: Comparison result

6 In Syndeia Dashboard in Containment Tree this is shown as below.

Figure 29: New blocks and proxy ports shown in SysML containment tree

 

Demonstration 3: Recursive Settings

3A) Generate SysML blocks with Full Ports and Apply

1 Set SysML port type when generating from Simulink setting to FULL_PORT under MATLAB/Simulink category in Syndeia settings, and click the Apply button.

Figure 30: Syndeia Settings tab

2 In Syndeia Dashboard perform Model Transform.Send System.slx to SysML Package From_Simulink>Recursive>FullPort

Figure 31: Model transform of System Simulink model to SysML package From_Simulink::Immediate::FullPort

3 In Syndeia Dashboard this appears as below.

Figure 32: New blocks and full ports shown in Syndeia dashboard

4 In the Connections Search tab click Get All. The connections generated are displayed. Select Compare Source and Target on the connection as shown below.

Figure 33: Compare Source and Target from Connection Search tab

5 The Comparison Result tab shows the result as below.

Figure 34: Comparison result

6 In SysML Containment Tree it appears as Full Port.

Figure 35: New blocks and full ports shown in SysML containment tree

 

3B) Generate SysML blocks with Proxy Ports and Apply

1 Set SysML port type when generating from Simulink setting to PROXY_PORT under MATLAB/Simulink category in Syndeia settings, and click the Apply button.

Figure 36: Syndeia Settings tab

 

2 In Syndeia Dashboard perform Model Transform.Send System.slx to SysML Package From_Simulink>Recursive>ProxyPort

Figure 37: Model transform of System Simulink model to SysML package From_Simulink::Recursive::ProxyPort

 

3 In Syndeia Dashboard in Connection Manager this appears as below.

Figure 38: New blocks and proxy ports shown in Syndeia dashboard

 

4 In the Connections Search tab click Get All. The connections generated are displayed. Select Compare Source and Target as shown below.

Figure 39: Compare Source and Target from Connection Search tab

 

5 In the Comparison Result tab the result is shown below.

Figure 40: Comparison result

 

6 In SysML Containment Tree it appears as Full Port.

Figure 41: New blocks and proxy ports shown in SysML containment tree

 

Summary

Three different settings of Simple, Immediate, and Recursive were introduced and demonstrated.

Drag-and-drop from Simulink to SysML and show the resulting SysML model based on that setting. Note that the setting for generating a full/proxy port will be used to decide the type of port generated on the SysML block.

Compare, Sync operation is common to all three settings.