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Exercise 10.6 - Simulink -> SysML with model generation level settings.

Exercise 10.6 - Simulink -> SysML with model generation level settings.

Objective

This tutorial demonstrates Simulink to SysML model generation level using the model generation and compare/sync between SysML and Simulink models. The three settings are as follows:

SysML from/to Simulink model generation level

Sets the level of model generation and compare/sync between SysML and Simulink models. The three settings are as follows:

(1) SIMPLE

  • SysML → Simulink: Generate a Simulink model based on the SysML Block/Activity. Only ports are generated. No internal structure is generated.

  • Simulink → SysML: Generate a SysML Block/Activity based on the Simulink model. Only ports are generated. No internal structure is generated.

(2) IMMEDIATE

  • SysML → Simulink: Generate a Simulink model based on the SysML Block/Activity. Simulink model will have ports corresponding to the SysML Block/Activity, and Simulink blocks and signal/bus flows corresponding to the immediate structure (1 level only) of the SysML Block/Activity, i.e. immediate part/reference/shared properties of the SysML Block, or immediate call behavior actions of the SysML Activity.

  • Simulink → SysML: Generate a SysML Block/Activity based on the Simulink model. SysML model will have ports (or pins) corresponding to the Simulink model, and part properties (or call behavior actions) and connectors (or object flows) corresponding to the immediate blocks (1 level only) and signal/bus flows in the Simulink model.

(3) RECURSIVE (default)

  • SysML → Simulink: Generate a Simulink model based on the SysML Block/Activity. Simulink model will have ports corresponding to the SysML Block/Activity, and Simulink blocks and signal/bus flows corresponding to all the part/reference/shared properties (or call behavior actions) in the multi-level SysML Block/Activity hierarchy.

  • Simulink → SysML: Generate a SysML Block/Activity based on the Simulink model. SysML model will have ports (or pins) corresponding to the Simulink model, and part properties (or call behavior actions) and connectors (or object flows) corresponding to all the blocks in the multi-level Simulink model hierarchy.

Preparation

This exercise assumes the student has

  • Rhapsody supported version installed correctly on his or her machine with a valid license for use.

  • Syndeia installed as a plugin for Rhapsody with a valid license for use.

  • Syndeia Simulink interface, correctly installed with a valid license for use.

  • MATLAB/Simulink R2016b or later installed correctly on his or her machine with a valid license for use.

  • In this tutorial, we will use the Simulink Model developed Exercise 10.5 - SysML -> Simulink with model generation level settings. in Demonstration 3 using Recursive settings.

This model will be sent to SysML using the three settings of Simple, Immediate, and Recursive.

The Simulink model is as shown here.

Figure 1: System Model in Simulink

The Target SysML Model and Package are in Syndeia_Simulink_Examples.rpyx (Get it here - SysML Models, Profiles and Mappings.) as shown here.

Figure 2: Target SysML model and packages

Demonstration 1: Simple Settings

1A) Generate SysML blocks with full ports

1 Set SysML port type when generating from Simulink setting to FULL_PORT under MATLAB/Simulink category in Syndeia settings, and click the Apply button.

Figure 3: Syndeia Settings tab

2 In Syndeia dashboard perform Model Transformation. Send System.slx to SysML Rhaspody Package FromSimulink>Simple>FullPort

Figure 4: Model Transform System from Simulink to SysML to generate internal block structure

3 In Rhapsody SysML Full Ports are generated as per type selected.

Figure 5: SysML blocks and full ports created from Simulink

4. Now going to Connections Search Tab in Syndeia and Click Get All to see the connections. Select Compare Source and Target.

Figure 6: Comparing Source and Target from Connection Search Tab

5 Ports are shown on both SysML as well as Simulink

Figure 7: Comparison result

6 Now in Simulink Model we add a new port ‘p1’ and remove the port in1 and further replace ‘in1’ with p1.

So Part A has p1 coming in.

Figure 8: Making changes in the Simulink model

7 Compare the connection again as in Step 4 above and see the result in Comparison Result.

Figure 9: Comparison result showing mismatch between ports in Simulink and SysML

Here p1 is shown on Simulink Side and in1 in on SysML side.

8 Now Sync Target and Source from Connections Search as shown below for the connection.

Figure 10: Syncing Target to Source from Connection Search tab

 

9 Again do Compare and can see p1 is appeared both on SysML and Simulink side.

Figure 11: Comparison result

10 In SysML Rhapsody Model it is seen as below.

Figure 12: SysML model updated

 

1B) Generate SysML blocks with Proxy Ports and Apply

1 Set SysML port type when generating from Simulink setting to PROXY_PORT under MATLAB/Simulink category in Syndeia settings, and click the Apply button.

Figure 13: Syndeia Settings tab

2 In the Syndeia dashboard perform Model Transformation. Send System.slx to SysML Package FromSimulink>Simple>ProxyPort

Figure 14: Model transform System Simulink model to SysML package From_Simulink::Simple::ProxyPort

3 In Syndeia it appears as below.

Figure 15: New System block and proxy ports shown in Syndeia dashboard

4 In Connections Search Tab in Syndeia again Select Compare for the connection, it appears as Proxy Port.

Figure 16: Comparison result

5 In SysML Rhapsody it is seen as Proxy Port.

Figure 17: New System block and proxy ports shown in SysML containment tree

 

Demonstration 2: Immediate Settings

2A) Generate SysML blocks with Full Ports and Apply

1 Set SysML port type when generating from Simulink setting to FULL_PORT under MATLAB/Simulink category in Syndeia settings, and click the Apply button.

Figure 18: Syndeia Settings tab

2 Perform Model Transform in Syndeia Dashboard. Send System.slx to SysML Package FromSimulink>Immediate>Full Port Im

Figure 19: Model Transformation to SysML package From_Simulink::Immediate Package::FullPort Im

3 In Syndeia Dashboard it appears as below.

Figure 20: Syndeia Dashboard showing blocks generated in SysML

4 Now going to Connections Search Tab in Syndeia and Click Get All to see the connections. Select Compare Source and Target.

Figure 21: Compare Source and Target from Connection Search tab

5 In Comparison Result this appears as below.

Figure 22: Comparison result

6 In SysML Rhapsody this looks as showing Full Ports.

Figure 23: New blocks and full ports shown in SysML containment tree

 

2B) Generate SysML blocks with Proxy Ports and Apply

1 Set SysML port type when generating from Simulink setting to PROXY_PORT under MATLAB/Simulink category in Syndeia settings, and click the Apply button.

Figure 24: Syndeia Settings tab

 

2 Perform Model Transform in Syndeia Dashboard. Send System.slx to SysML Package FromSimulink>Immediate>Proxy Port Im

Figure 25: Model transform of System Simulink model to SysML package From_Simulink::Immediate::ProxyPort Im

3 In Syndeia Dashboard this appears as below.

Figure 26: New blocks and proxy ports shown in Syndeia dashboard

4 Now going to Connections Search Tab in Syndeia and Click Get All to see the connections. Select Compare Source and Target and result will appear in Comparison Result as below.

Figure 27: Comparison result

5 In SysML Rhapsody it appears as Proxy Port as shown below.

Figure 28: New blocks and proxy ports shown in SysML containment tree

 

Demonstration 3: Recursive Settings

3A) Generate SysML blocks with Full Ports and Apply

1 Set SysML port type when generating from Simulink setting to FULL_PORT under MATLAB/Simulink category in Syndeia settings, and click the Apply button.

Figure 29: Syndeia Settings tab

2 In Syndeia Dashboard perform Model Transform send System.slx to SysML Package FromSimulink>Recursive>Full Port Rc

Figure 30: Model transform of System Simulink model to SysML package From_Simulink::Immediate::Full Port Rc

3 In Syndeia this looks like as shown below.

Figure 31: New blocks and full ports shown in Syndeia dashboard

4 Now going to Connections Search Tab in Syndeia and Click Get All to see the connections. Select Compare Source and Target.

Figure 32: Compare Source and Target from Connection Search tab

5 Comparison Result shows as below.

Figure 33: Comparison result

6 In Rhapsody this appears as Full Ports as shown below.

Figure 34: New blocks and full ports shown in SysML containment tree

3B) Generate SysML blocks with Proxy Ports and Apply

1 Set SysML port type when generating from Simulink setting to PROXY_PORT under MATLAB/Simulink category in Syndeia settings, and click the Apply button.

Figure 35: Syndeia Settings tab

2 In Syndeia Dashboard perform Model Transform.Send System.slx to SysML Package FromSimulink>Recursive>Proxy Port Rc

Figure 36: Model transform of System Simulink model to SysML package From_Simulink::Recursive::Proxy Port Rc

3 In Syndeia Dashboard appears as below.

Figure 37: New blocks and proxy ports shown in Syndeia dashboard

4 Now going to Connections Search Tab in Syndeia and Click Get All to see the connections. Select Compare Source and Target.

Figure 38: Compare Source and Target from Connection Search tab

5 Compare Result shows as below in the Comparison Result tab.

Figure 39: Comparison result

6 In Rhapsody this appears as below.

Figure 40: New blocks and proxy ports shown in SysML containment tree

Summary

Three different settings of Simple, Immediate, and Recursive were introduced and demonstrated.

Drag-and-drop from Simulink to SysML Rhapsody and showing the resulting SysML Rhapsody model based on that setting. Note that the setting for generating full/proxy port will be used to decide the type of port generated on the SysML Rhapsody block.

Compare, Sync operation is common to all three settings.